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1 ?1999 integrated device technology, inc. december 1999 dsc-3822/03 zbt and zero bus turnaround are trademarks of integrated device technology, inc. and the architecture is supported by micron te chnology and motorola inc. idt71v547 pin description summary the idt71v547 contains address, data-in and control signal registers. the outputs are flow-through (no output data register). output enable is the only asynchronous signal and can be used to disable the outputs at any given time. a clock enable ( cen ) pin allows operation of the idt71v547 to be suspended as long as necessary. all synchronous inputs are ignored when cen is high and the internal device registers will hold their previous values. there are three chip enable pins ( ce 1 , ce 2 , ce 2 ) that allow the user to deselect the device when desired. if any one of these three is not active when adv/ ld is low, no new memory operation can be initiated and any burst in progress is stopped. however, any pending data transfers (reads or writes) will be completed. the data bus will tri-state one cycle after the chip was deselected or write initiated. the idt71v547 has an on-chip burst counter. in the burst mode, the idt71v547 can provide four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the lbo input pin. the lbo pin selects between linear and interleaved burst sequence. the adv/ ld signal is used to load a new external address (adv/ ld = low) or increment the internal burst counter (adv/ ld = high). the idt71v547 sram utilizes idt's high-performance, high-volume 3.3v cmos process, and is packaged in a jedec standard 14mm x 20mm 100-pin thin plastic quad flatpack (tqfp) for high board density. features u u u u u 128k x 36 memory configuration, flow-through outputs u u u u u supports high performance system speed - 95 mhz (8ns clock-to-data access) u u u u u zbt tm feature - no dead cycles between write and read cycles u u u u u internally synchronized signal eliminates the need to control oe oe oe oe oe u u u u u single r/ w w w w w (read/write) control pin u u u u u 4-word burst capability (interleaved or linear) u u u u u individual byte write ( bw bw bw bw bw 1 - bw bw bw bw bw 4 ) control (may tie active) u u u u u three chip enables for simple depth expansion u u u u u single 3.3v power supply (5%) u u u u u packaged in a jedec standard 100-pin tqfp package description the idt71v547 is a 3.3v high-speed 4,718,592-bit (4.5 megabit) synchronous sram organized as 128k x 36 bits. it is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. thus it has been given the name zbt tm , or zero bus turn-around. address and control signals are applied to the sram during one clock cycle, and on the next clock cycle, its associated data cycle occurs, be it read or write. 128k x 36, 3.3v synchronous sram with zbt? feature, burst counter and flow-through outputs a 0 - a 16 address inputs input synchronous ce 1 , ce 2 , ce 2 three chip enables input synchronous oe output enable input asynchronous r/ w read/write signal input synchronous cen clock enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 individual byte write selects input synchronous clk clock input n/a adv/ ld advance burst address / load new address input synchronous lbo linear / interleaved burst order input static i/o 0 - i/o 31 , i/o p1 - i/o p4 data input/output i/o synchronous v dd 3.3v power supply static v ss ground supply static 3822 tbl 01
2 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk. symbol pin function i/o active description a 0 - a 16 address inputs i n/a synchronous address inputs. the address register is triggered by a combination of the rising edge of clk, adv/ ld low, cen low and true chip enables. adv/ ld address/load i n/a adv/ ld is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. when adv/ ld is low with the chip deselected, any burst in progress is terminated. when adv/ ld is sampled high then the internal burst counter is advanced for any burst that was in progress. the external addresses are ignored when adv/ ld is sam pled high. r/ w read/write i n/a r/ w signal is a synchronous input that identifies whether the current load cycle initiated is a read or write access to the memory array. the data bus activity for the current cycle takes place one clock cycle later. cen clock enable i low synchronous clock enable input. when cen is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. the effect of cen sampled high on the device outputs is as if the low to high clock transition did not occur. for normal operation, cen must be sampled low at rising edge of clock. bw 1 - bw 4 individual byte write enables i low synchronous byte write enables. enable 9-bit byte has its own active low byte write enable. on load write cycles (when r/ w and adv/ ld are sampled low) the appropriate byte write signal ( bw 1 - bw 4 ) must be valid. the byte write signal must also be valid on each cycle of a burst write. byte write signals are ignored when r/ w is sampled high. the appropriate byte(s) of data are written into the device one cycle later. bw 1 - bw 4 can all be tied low if always doing write to the entire 36-bit word. ce 1 , ce 2 chip enables i low synchronous active low chip enable. ce 1 and ce 2 are used with ce 2 to enable the idt71v547. ( ce 1 or ce 2 sampled high or ce 2 sampled low) and adv/ ld low at the rising edge of clock, initiates a deselect cycle. this device has a one cy cle deselect, i.e., the data bus will tri-state one clock cycle after deselect is initiated. ce2 chip enable i high synchronout active high chip enable. ce 2 is used with ce 1 and ce 2 to enable the chip. ce 2 has inverted polarity but otherwise identical to ce 1 and ce 2 . clk clock i n/a this is the clock input to the idt71v547. except for oe , all timing references for the device are made with respect to the rising edge of clk. i/o 0 - i/o 31 i/o p1 - i/o p4 data input/output i/o n/a data input/output (i/o) pins. the data input path is registered, triggered by the rising edge of clk. the data output path is flow-through (no output register). lb o linear burst order i low burst order selection input. when lb o is high the interleaved burst sequence is selected. when lb o is low the linear burst sequence is selected. lb o is a static dc input. oe output enable i low asynchronous output enable. oe must be low to read data from the 71v547. when oe is high the i/o pins are in a high-impedance state. oe does not need to be actively controlled for read and write cycles. in normal operation, oe can be tied low. v dd power supply n/a n/a 3.3v power supply input. v ss ground n/a n/a ground pin. 3822 tbl 02
6.42 3 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges functional block diagram recommended operating temperature and supply voltage recommended dc operating conditions clk dq dq dq address a [0:16] control logic address control di do input r egister 3822 drw 01 clock data i/o [0:31], i/o p[1:4] mux sel gate oe ce 1 ,ce2 ce 2 r/ w cen adv/ ld bw x lb o 128k x 36 bit memory array , notes: 1. v il (min.) = C1.0v for pulse width less than t cyc /2, once per cycle. 2. v ih (max.) = +6.0v for pulse width less than t cyc /2, once per cycle. grade temperature v ss v dd commercial 0 o c to +70 o c0v 3.3v5% industrial -40 o c to +85 o c0v 3.3v5% 38 22 tbl 03 symbol parameter min. typ. max. unit v dd supply voltage 3.135 3.3 3.465 v v ss ground 0 0 0 v v ih input high voltage - inputs 2.0 ____ 4.6 v v ih input high voltage - i/o 2.0 ____ v dd +0.3 (2) v v il input low voltage -0.5 (1) ____ 0.8 v 38 22 tbl 04
4 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges absolute maximum ratings (1) pin configuration capacitance (t a = +25c, f = 1.0mhz, tqfp package) notes: 1. pin 14 does not have to be connected directly to v ss as long as the input voltage is < v il . 2. pins 83 and 84 are reserved for future a 17 (8m) and a 18 (16m) respectively. 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e 1 c e 2 b w 2 b w 1 c e 2 v d d v s s c lk r / w c e n o e a d v / ld n c (2) n c (2) a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n c n c n c n c lb o a 14 a 13 a 12 a 11 a 10 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 v dd v ss v ss v dd i/o 27 i/o 26 v ss v dd i/o 25 i/o 24 v dd v ss v ss v dd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 v dd v ss i/o 23 i/o 22 v ss v dd i/o 21 i/o 20 v ss v dd i/o 11 i/o 10 v dd v ss i/o 9 i/o 8 i/o 7 i/o 6 v ss v dd i/o 5 i/o 4 pk100-1 3822 drw 02 v ss (1) v dd a 15 a 16 i/o 12 i/o 28 v ss v ss b w 4 b w 3 i/o p2 i/o 14 i/o 15 i/o 13 i/o 2 i/o 3 i/o p1 i/o 0 i/o 1 i/o p4 i/o 30 i/o 31 i/o 29 i/o 19 i/o 18 i/o p3 i/o 16 i/o 17 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd and input terminals only. 3. i/o terminals. note: 1. this parameter is guaranteed by device characterization, but not production tested. symbol rating value unit v te rm (2 ) te r m i n a l vo l ta g e with respect to gnd -0.5 to +4.6 v v te rm (3 ) te r m i n a l vo l ta g e with respect to gnd -0.5 to v dd +0.5 v t a operating temperature 0 to +70 o c t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 2.0 w i out dc output current 50 ma 3 822 tb l 05 symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 5 pf c i/o i/o capacitance v out = 3dv 7 pf 3822 tbl 06 top view tqfp
6.42 5 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges partial truth table for writes (1) synchronous truth table (1) notes: 1. l = v il , h = v ih , x = dont care. 2. when adv/ ld signal is sampled high, the internal burst counter is incremented. the r/ w signal is ignored when the counter is advanced. therefore the nature of the burst cycle (read or write) is determined by the status of the r/ w signal when the first address is loaded at the beginning of the burst cycle. 3. deselect cycle is initiated when either ( ce 1 , or ce 2 is sampled high or ce 2 is sampled low) and adv/ ld is sampled low at rising edge of clock. the data bus will tri-state one cycle after deselect is initiated. 4. when cen is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. the state of all t he internal registers and the i/os remains unchanged. 5. to select the chip requires ce 1 = l, ce 2 = l and ce 2 = h on these chip enable pins. the chip is deselected if either one of thechip enable is false. 6. device outputs are ensured to be in high-z during device power-up. 7. q - data read from the device, d - data written to the device. cen r/ w chip (5 ) enable adv/ ld bw x address used previouis cycle current cycle i/o (1 cycle later) l l select l valid external x load write d (7 ) l h select l x external x load read q (7 ) l x x h valid internal load write/ burst write burst write (advance burst counter) (2 ) d (7 ) l x x h x internal load read/ burst read burst read (advance burst counter) (2 ) q (7 ) l x deselect l x x x deselect or stop (3 ) hiz l x x h x x deselect / noop noop hiz h x x x x x x suspend (4 ) previous value 3822 tbl 07 notes: 1. l = v il , h = v ih , x = dont care. 2. multiple bytes may be selected during the same cycle. operation r/ w bw 1 bw 2 bw 3 bw 4 read hxxxx write all bytes l l l l l write byte 1 (i/o [0:7], i/o p1 ) (2) llhhh write byte 2 (i/o [8:15], i/o p2 ) (2) lhlhh write byte 3 (i/o [16:23], i/o p3 ) (2) lhhlh write byte 4 (i/o [24:31], i/o p4 ) (2) lhhhl no write lhhhh 3822 tbl 08
6 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges functional timing diagram (1) note: 1. this assumes cen , ce 1 , ce2 and ce 2 are all true. 2. all address, control and data_in are only required to meet set-up and hold time with respect to the rising edge of clock. da ta_out is valid after a clock-to-data delay from the rising edge of clock. n+29 a29 c29 d/q28 address (a0 - a16) control (r/ w ,adv/ ld , bw x) data i/o [0:31], i/o p[1:4] cycle clock n+30 a30 c30 d/q29 n+31 a31 c31 d/q30 n+32 a32 c32 d/q31 n+33 a33 c33 d/q32 n+34 a34 c34 d/q33 n+35 a35 c35 d/q34 n+36 a36 c36 d/q35 (2) (2) (2) 3822 drw 03 a37 c37 d/q36 n+37 ., linear burst sequence table ( lbo =v ss ) interleaved burst sequence table ( lbo =v dd ) note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address00011011 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11 10 01 00 3822 tbl 09 note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11 00 01 10 3822 tbl 10
6.42 7 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges note: 1. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. 2. h = high; l = low; x = don't care; z = high impedence. device operation - showing mixed load, burst, deselect and noop cycles (2) cycle address r/ w adv/ ld ce (1) cen bw x oe i/o comments na0hlllxxd1load read n+1 x x h xlxlq0burst read n+2 a1 h l l l x l q 0+1 load read n+3 x x l h l x l q1 deselect or stop n+4 x x h x l x x z noop n+5 a2 h l l l x x z load read n+6 x x h xlxlq2burst read n+7 x x l h l x l q 2+1 deselect or stop n+8 a3 l l l l l x z load write n+9 x x h x l l x d3 burst write n+10 a4 l l l l l x d 3+1 load write n+11 x x l h l x x d4 deselect or stop n+12 x x h x l x x z noop n+13 a5 l l l l l x z load write n+14 a6 h l l l x x d5 load read n+15 a7 l l l l l l q6 load write n+16 x x h x l l x d7 burst write n+17 a8 h l l l x x d 7+1 load read n+18 x x h x l x l q8 burst read n+19 a9 l l l l l l q 8+1 load write 3822 tbl 11
8 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges read operation (1) note: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. burst write operation (1) note: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. burst read operation (1) note: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce2 timing transition is identical but inverted to the ce 1 and ce 2 signals. write operation (1) note: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 h l l l x x x address and control meet setup n+1 x x x x x x l q0 contents of address a0 read out 3822 tbl 12 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 h l l l x x x address and control m eet setup n+1 x x h x l x l q0 address a0 read out, inc. count n+2 x x h x l x l q 0+1 address a 0+1 read out, inc. count n+3 x x h x l x l q 0+2 address a 0+2 read out, inc. count n+4 x x h x l x l q 0+3 address a 0+3 read out, load a1 n+5 a1 h l l l x l q0 address a0 read out, inc. count n+6 x x h x l x l q1 address a1 read out, inc. count n+7 a2 h l l l x l q 1+1 address a 1+1 read out, load a2 3822 tbl 13 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 l l l l l x x address and control meet setup n+1 x x x x l x x d0 write to address a0 3822 tbl 14 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 l l l l l x x address and control meet setup n+1 x x h x l l x d0 address a0 write, inc. count n+2 x x h x l l x d 0+1 address a 0+1 write, inc. count n+3 x x h x l l x d 0+2 address a 0+2 write, inc. count n+4 x x h x l l x d 0+3 address a 0+3 write, load a1 n+5 a1 l l l l l x d0 address a0 write, inc. count n+6 x x h x l l x d1 address a1 write, inc. count n+7 a2 l l l l l x d 1+1 address a 1+1 write, load a2 3822 tbl 15
6.42 9 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges note: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. read operation with clock enable used (1) note: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. write operation with clock enable used (1) cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 h l l l x x x address and control m eet setup n+1 x x x x h x x x clock n+1 ignored n+2 a1 h l l l x l q0 address a0 read out, load a1 n+3 x x x x h x l q0 clock ignored. data q0 is on the bus n+4 x x x x h x l q0 clock ignored. data q0 is on the bus n+5 a2 h l l l x l q1 address a1 read out, load a2 n+6 a3 h l l l x l q2 address a2 read out, load a3 n+7 a4 h l l l x l q3 address a3 read out, load a4 3822 tbl 16 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 l l l l l x x address and control meet setup n+1 x x x x h x x x clock n+1 ignored n+2 a1 l l l l l x d0 write data d0, load a1 n+3 x x x xhxxxclock ignored n+4 x x x xhxxxclock ignored n+5 a2 l l l l l x d1 write data d1, load a2 n+6 a3 l l l l l x d2 write data d2, load a3 n+7 a4 l l l l l x d3 write data d3, load a4 3822 tbl 17
10 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges notes: 1. h = high; l = low; x = dont care; ? = don't know; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. 3. device outputs are ensured to be in high-z during device power-up. read operation with chip enable used (1) notes: 1. h = high; l = low; x = dont care; ? = don't know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. write operation with chip enable used (1) cycle address r/ w adv/ ld ce (1) cen bw x oe i/o (3) comments n x x l h l x x ? deselected n+1 x x l h l x x z deselected n+2 a0 h l l l x x z address a0 and control meet setup n+3 x x l h l x l q0 address a0 read out. deselected n+4 a1 h l l l x x z address a1 and control meet setup n+5 x x l h l x l q1 address a1 read out. deselected n+6 x x l h l x x z deselected n+7 a2 h l l l x x z address a2 and control meet setup n+8 x x l h l x l q2 address a2 read out. deselected n+9 x x l h l x x z deselected 3822 tbl 18 cycle address r/ w adv/ ld ce (1 ) cen bw x oe i/o comments n x x l h l x x ? deselected n+1 x x l h l x x z deselected n+2 a0 l l l l l x z address a0 and control m eet setup n+3 x x l h l x x d0 address d0 write in. deselected n+4 a1 l l l l l x z address a1 and control m eet setup n+5 x x l h l x x d1 address d1 write in. deselected n+6 x x l h l x x z deselected n+7 a2 l l l l l x z address a2 and control m eet setup n+8 x x l h l x x d2 address d2 write in. deselected n+9 x x l h l x x z deselected 3822 tbl 19
6.42 11 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges symbol parameter test conditions s80 s85 s90 s100 unit com'l ind com'l ind com'l ind com'l ind i dd operating power supply current device selected, outputs open, adv/ ld = x, v dd = max., v in > v ih or < v il , f = f max (2) 250 260 225 235 225 235 200 210 ma i sb1 cmos standby power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = 0 (2) 40 45 40 45 40 45 40 45 ma i sb2 clock running power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = f max (2) 100 110 95 105 95 105 90 100 ma i sb3 idle power supply current device selected, outputs open, cen > v ih v dd = max., v in > v hd or < v ld , f = f max (2) 40 45 40 45 40 45 40 45 ma 3822 tbl 21 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v +/-5%) figure 2. lumped capacitive load, typical derating figure 1. ac test load ac test loads ac test conditions dc electrical characteristics over the operating temperature and supply voltage range (1) (v dd = 3.3v +/-5%, v hd = v dd ?0.2v, v ld = 0.2v) 1.5v 50 w i/o z 0 =50 w 3822 drw 04 + , 1 2 3 4 20 30 50 100 200 d tcd (typical, ns) capacitance (pf) 80 5 6 3822 drw 05 . note: 1. the lbo pin will be internally pulled to v dd if it is not actively driven in the application. symbol parameter test conditions min. max. unit |i li | input leakage current v dd = max., v in = 0v to v dd ___ 5a |i li | lbo input leakage current (1) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current ce > v ih or oe > v ih , v out = 0v tov dd , v dd = max. ___ 5a v ol output low voltage i ol = 5ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -5ma, v dd = min. 2.4 ___ v 3822 tbl 20 notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc ; f=0 means no input lines are changing. input pulse levels input rise/fall times input timing reference levels output timing reference levels ac test load 0 to 3v 2ns 1.5v 1.5v see figure 1 38 22 tbl 22
12 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges ac electrical characteristics (v dd = 3.3v +/-5%, commercial and industrial temperature ranges) notes: 1. measured as high above 2.0v and low below 0.8v. 2. transition is measured 200mv from steady-state. 3. these parameters are guaranteed with the ac load (figure 1) by device characterization. they are not production tested. 4. to avoid bus contention, the output buffers are designed such that t chz (device turn-off) is about 2 ns faster than t clz (device turn-on) at a given temperature and voltage. the specs as shown do not imply bus contention because t clz is a min. parameter that is worse case at totally different test conditions (0 deg. c, 3.465v) than t chz , which is a max. parameter (worse case at 70 deg. c, 3.135v). . symbol parameter 71v547s80 71v547s85 71v547s90 71v547s100 unit min. max. min. max. min. max. min. max. clock parameters t cy c clock cycle time 10.5 ____ 11 ____ 12 ____ 15 ____ ns t ch (2 ) clock high pulse width 3 ____ 3.9 ____ 4 ____ 5 ____ ns t cl (2 ) clock low pulse width 3 ____ 3.9 ____ 4 ____ 5 ____ ns output parameters t cd clock high to valid data ____ 8 ____ 8.5 ____ 9 ____ 10 ns t cdc clock high to data change 2 ____ 2 ____ 2 ____ 2 ____ ns t cl z (3 , 4,5) clock high to output active 4 ____ 4 ____ 4 ____ 4 ____ ns t chz (3 , 4,5) clock high to data high-z ____ 5 ____ 5 ____ 5 ____ 5ns t oe output enable access time ____ 5 ____ 5 ____ 5 ____ 5ns t ol z (3,4) output enab l e low to data active 0 ____ 0 ____ 0 ____ 0 ____ ns t ohz (3.4) output enable high to data high-z ____ 5 ____ 5 ____ 5 ____ 5ns setup times t se clock enable setup time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns t sa address setup time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns t sd data in setup time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns t sw read/write (r/ w ) setup time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns t sadv advance/load (adv/ ld ) setup time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns t sc chip enable/select setup time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns t sb byte write enable ( bw x) setup time 2.0 ____ 2.0 ____ 2.0 ____ 2.5 ____ ns hold times t he clock enable hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t hd data in hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t hw read/write (r/ w ) hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t hadv advance/load (adv/ ld ) hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t hb byte write enable ( bw x) hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns 3822 tbl 23
6.42 13 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges timing waveform of read cycle (1, 2, 3, 4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . q (a 2 ) represents the first output from the external address a 2 ; q (a 2+1 ) represents the next output data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. ( c e n high, elim inates current l-h clock edge) q (a 2+1 ) tc d r ead tc lz tc h z tc d tc d c q (a 2+2 ) q (a 1) q (a 2) q (a 2+ 3 ) q (a 2+3 ) q (a 2) b urst r ead r ead d a t a o ut (b urst w raps around to initial state) tc d c th a d v 3822 drw 06 r / w c lk c e n a d v / ld a d d r e s s c e 1 , c e 2 ( 2) b w 1 - b w 4 o e th e ts e a 1 a 2 tc h tc l tc y c ts a d v th w ts w th a ts a th c ts c ,
14 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges timing waveform of write cycles (1,2,3,4,5) notes: 1. d (a 1 ) represents the first input to the external address a 1 . d (a 2 ) represents the first input to the external address a 2 ; d (a 2+1 ) represents the next input data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. 5. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. th e ts e r / w a 1 a 2 c lk c e n a d v / ld a d d r e s s c e 1 , c e 2 (2) b w 1 - b w 4 o e d a t a in d (a 1) d (a 2) th d ts d ( c e n high, elim inates current l-h clock edge) d (a 2+ 1 ) d (a 2+2 ) d (a 2+ 3 ) d (a 2) b urst w rite w rite w rite (b urst w raps around to initial state) th d ts d tc h tc l tc y c th a d v ts a d v th w ts w th a ts a th c ts c th b ts b 3822 drw 07 b (a 1) b (a 2) b (a 2+1 ) b (a 2+ 2 ) b (a 2+3 ) b (a 2) .
6.42 15 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges timing waveform of combined read and write cycles (1,2,3) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. th e ts e r / w a 1 a 2 c lk c e n a d v / ld a d d r e s s c e 1 , c e 2 (2) b w 1 - b w 4 o e d a t a o ut q (a 3) q (a 1) q (a 6) q (a 7) tc d r ead r ead r ead r ead tc h z 3822 drw 08 w rite tc lz d (a 2) d (a 4) tc d c d (a 5) w rite tc h tc l tc y c th w ts w th a ts a a 4 a 3 th c ts c ts d th d th a d v ts a d v a 6 a 7 a 8 a 5 a 9 d a t a in th b ts b w rite d (a 8) w rite b (a 2) b (a 4) b (a 5) b (a 8) ,
16 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges timing waveform of cen operation (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high.. 3. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propogating into the sram. the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous state. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. th e ts e r / w a 1 a 2 c lk c e n a d v / ld a d d r e s s c e 1 , c e 2(2) b w 1 - b w 4 o e d a t a o ut q (a 1) tc d c q (a 3) tc d tc lz q (a 1) q (a 4) tc d tc d c tc h z d (a 2) ts d th d tc h tc l tc y c th c ts c a 4 a 5 th a d v ts a d v th w ts w th a ts a a 3 th b ts b d a t a in 3822 drw 09 b (a 2) ,
6.42 17 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges timing waveform of cs operation (1,2,3,4) notes: 1. q (a1) represents the first output from the external address a1. d (a3) represents the input data to the sram corresponding to address a3 etc. 2. ce2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce2 is high. 3. when either one of the chip enables ( ce 1, ce2, ce 2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. the data-bus tri-states one cycle after the in itiation of the deselect cycle. this allows for any pending data transfers (reads or writes) to be completed. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. r / w a 1 c lk a d v / ld a d d r e s s c e 1 , c e 2(2) o e d a t a o ut q (a 1) q (a 2) q (a 4) tc lz q (a 4) tc d tc h z tc d c d (a 3) ts d th d tc h tc l tc y c th c ts c a 5 a 3 ts b d a t a in th e ts e a 2 th a ts a a 4 th w ts w th b c e n th a d v ts a d v 3822 drw 10 b w 1 - b w 4 b (a 3) .
18 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges timing waveform of oe operation (1) note: 1. a read operation is assumed to be in progress. ordering information oe data out tohz tolz toe q q . 3822 drw 11 plastic thin quad flatpack, 100 pin (pk100-1) s power xx speed pf package pf idt 71v547 80 85 90 100 access time (t cd ) in tenths of nanoseconds 3822 drw 12 device type part number t cd parameter 71v547s80pf 71v547s85pf 71v547s90pf 71v547s100pf 95 mhz 90 mhz 83 mhz 66 mhz 8ns 8.5 ns 9ns 10 ns 10.5 ns 11 ns 1 2ns 15 ns speed in megahertz clock cycle time x process/ temperature range commercial (0c to +70c) industrial (-40c to +85c) blank i
6.42 19 idt71v547, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and flow-through outputs commercial and industrial temperature ranges corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax: 408-492-8674 800-544-7726, x4033 www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 6/15/99 updated to new format 9/13/99 pg. 11 corrected i sb3 conditions pg. 19 added datasheet document history 12/31/99 pp. 3, 11, 12, 18 added industrial temperature range offerings

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